1. Field of the Invention
The present invention relates to frequency synthesizer circuits, and more particularly to frequency synthesizer circuits used in data storage systems such as, for example, magnetic disk storage systems.
2. Description of Related Art
In data storage systems data is stored on a storage media such as a CD-ROM, writable CD, DVD or other optical disk, magnetic tape, magnetic hard disk, etc. Typically, when data is read from the storage media, some form of data detection circuitry is utilized to process the signal generated from or written to the storage media. In magnetic data storage systems, digital data serves to modulate the current in the read/write head coil so that a series of corresponding magnetic flux transitions may be written on to the medium. To read this recorded data, the read head passes over the medium and transduces the magnetic transitions into electrical pulses that alternate in polarity. These pulses are decoded by circuitry commonly called read/write channel circuitry to reproduce the digital data.
The storage medium generally contains at least two types of information or data. The first type of data may be called user data (sometimes referred to as just "data") and generally includes the data that an end user is saving or retrieving from the medium. The second type of information on the medium, called servo information or servo data, is used to determine the position of the read/write head on the medium. Servo information is generally embedded or written on the medium as part of the medium manufacturing process. Often, the two types of data stored on the medium are stored in alternating zones. For example, when information is to be obtained from the disk type medium it is generally transferred in alternating modes of operation, a "read operation" (for obtaining user data) and a "servo operation" (for obtaining servo information). When information is being transferred to a disk the mode of operation is generally called a "write operation."
Decoding the electrical pulses generated from a disk into a digital sequence is performed in most conventional designs by using a discrete time sequence detector in a sampled amplitude read channel. Discrete time sequence detectors are preferred to analog peak detect read channels since the discrete time systems can compensate for inter-symbol interference (ISI) and non-linearities in the medium, providing more reliable and robust data detection performance. There are several well known discrete time sequence detection methods for use in a sampled amplitude read/write channel circuit including discrete time pulse detection (DPD), partial response (PR) with Viterbi detection (partial response maximum likelihood (PRML) sequence detection), decision-feedback equalization (DFE), enhanced decision-feedback equalization (EDFE), and fixed-delay tree-search with decision-feedback (FDTS/DF).
The conversion of the continuous electrical pulses from the disk into a discrete sample sequence involves the "sampling" of the input sequence. The samples are generated at a known rate, known as the sampling rate. The sampling rate is at the frequency of the sampling clock, which is usually generated by a frequency synthesizer, which often contains a phase locked loop (PLL) operating at a programmable frequency. As an example, the clock output of a PLL used to generate the sampling clock for a read channel circuit might range from 50 to 250 MHz. The clock generated by the PLL is used to drive the sampling system, which converts the continuous electrical pulse to discrete sequence. In analog systems, the sampling system is usually a sample-and-hold (S/H) stage, whereas in digital systems, the sampling system is an analog-to-digital converter (ADC).
The actual frequency of the PLL is programmed to be the rate at which data is to be written to or read from the disk. In conventional magnetic storage systems, the rate at which the user data is stored on the medium varies depending upon the location of the data on the medium, while the servo rate is fixed for the entire magnetic medium. In read channel systems where the servo data is detected after conversion to a discrete sample sequence, there usually exist at least two PLL's, one operating at a frequency that corresponds to the data rate and the other operating at a frequency that corresponds to the servo rate. The read channel circuitry chooses the appropriate clock to drive the sampling operation depending on whether the servo information or the data information is being read. In addition, a third PLL may be provided to clock in the digital data to be written on to the magnetic medium and to transfer it to the read/write coil. These PLLs are thus utilized to generate the clock signals which drive the various read, servo and write circuits within a read/write channel circuit.
FIG. 1 illustrates a typical frequency synthesizer 100 which may be utilized to generate the read, write or servo clock of a read/write channel circuit. As shown in FIG. 1, the frequency synthesizer 100 is a phase lock loop (PLL) which may include a current controlled oscillator 102 and a reference clock input signal 104. The phase locking loop is completed by feeding back the output of the oscillator to a phase/frequency detector which also receives the reference clock signal. More particularly, the reference clock 104 is provided to a divider circuit 106 which divides the reference clock signal by a value of N. The output of the divider 106 is provided as one input to the phase/frequency detector 108. The output of the phase/frequency detector is provided to a charge pump 110 which in turn provides an output to a loop filter 112. The current output of the loop filter 112 is provided to the current controlled oscillator 102. The output 116 of the frequency synthesizer 100 is provided as an output clock and also utilized in a feedback loop which is provided to the divider 118 which divides the output 116 by M. The output of the divider 118 is then provided as the second input to the phase/frequency detector 108. Thus, the PLL receives a reference clock and modulates the control signal of a controlled oscillator until a divided-down version of the oscillator output clock matches in phase with a divided-down version of the reference clock. The loop is considered to be in phase-locked operation when the phases of these divided-down clocks match.
The reference clock is usually a low frequency clock in the range of 10 to 60 MHz generated from a crystal oscillator. The M and N values of the PLL may be called the PLL loop divisors since the output frequency at the PLL output 116 is F.sub.S, and is given by EQU F.sub.s =(M/N)F.sub.REF
where F.sub.REF is the reference clock frequency. The update rate of the PLL varies with the reference frequency and the divisor N (update rate=F.sub.REF .div.N). The loop control circuits (the phase/frequency detector 108, charge pump 110 and loop filter 112) operate at this update rate.
If M is greater than N, we can see that the output frequency of the clock from the PLL, F.sub.S, is greater than the input frequency to the PLL, F.sub.REF The generation of a higher output frequency is important in read/write channel applications, where data rates are quite high and also span a wide frequency range, for example from 50 to 250 MHz. Further, it is desirable to generate these frequencies that are much higher than the reference clock frequencies while maintaining low jitter within the output clock signal. Jitter, or phase noise, is the phase error in F.sub.S due to random phase variations around the ideal F.sub.S.
In read channel applications, the values of M and N of the PLL may be programmable to be able to achieve a wide range of values for F.sub.S. For example, a typical range for the loop divisors M and N may be any quantity from 1 to 255. Because M and N are discrete integer quantities, the PLL does not operate at any arbitrary frequency, but rather is limited to a discrete set of frequencies that are predictable for a known range of M and N values. The step that the synthesizer takes between two neighboring frequencies is known as the resolution of the synthesizer. The resolution of the synthesizer is generally determined by the upper end of the range of possible values for N. As the resolution of the PLL improves, the largest step between any two neighboring frequencies decreases. The resolution percentage of the synthesizer may be defined as the smallest frequency step as a percentage of F.sub.S. Thus, a higher resolution results in smaller frequency steps and a lower resolution percentage. In read channel applications, it is common to design PLL's with a frequency resolution of around 0.4% of F.sub.S, i.e. the next higher or lower frequency step is only a maximum of 0.4% of F.sub.S. For PLL's that need to operate from 50 to 250 MHz while utilizing a reference clock of 40 MHz, this means that the usable values of N might range between 1 and 125, implying a minimum update rate of 40 M/125=320 KHz. Since it is desirable to design the PLL to have a very high frequency resolution so that the data rates can be chosen to maximize the usage of the disk drives, it is desirable for the PLL to be implemented with sufficiently high values of N.
However, for lower update rates (i.e. larger N values), the loop control circuits (the phase/frequency detector 108, charge pump 110 and loop filter 112) will be operating at lower frequencies, thus requiring larger devices in the loop control circuits. This makes the PLL larger and the design more difficult. In addition, for large values of N, the loop control circuits generate corrections to the oscillator less frequently since the corrections occur at the update frequency F.sub.up. This implies that the oscillator is more likely to have errors in phase which manifests as phase noise, or jitter in the output clock, F.sub.S. Therefore to minimize jitter and to thus obtain less error in the read and write operations, it is desirable in read/write channel applications for PLL's to be designed at high update rates (lower N values).
Thus, in typical PLL designs a trade off exists between the desires for good frequency resolution performance and good jitter performance. It would be desirable to utilize a frequency synthesizer for read/write channel circuits which maximizes both frequency resolution and jitter performance.